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? 2015 microchip technology inc. ds20005412a-page 1 hv7351 features eight channels with return-to-zero (rtz) up to 70v output voltage 3.0a output current stores up to four different patterns independent programmable delays 80-lead single 11 x 11 mm vqfn package applications medical ultrasound imaging ndt, non-destructive testing arbitrary pattern generator high-speed pin diode driver general description the hv7351 device is an 8-channel programmable high-voltage ultrasound-transmit beamformer. each channel is capable of swinging up to 70v with an active discharge back to 0v. the outputs can source and sink up to 3.0a to achieve fast output rise and fall times. the active discharge is also capable of sourcing and sinking 3.0a for a fast return to ground. the topol- ogy of the hv7351 will significantly reduce the number of i/o logic control lines needed. each pulser has four associated 64-bit shift registers for storing predetermined transmit patterns and a 10-bit delay counter for controlling the transmit time. one of four arbitrary patterns can be transmitted with adjust- able delay, depending on the data loaded into these shift registers and the delay counter. the delay counter can be clocked up to 200 mhz, allowing incremental delays down to 5 ns. typical application circuit tx128 trig tx127 tx3 tx2 tx1 t delay1 trig hv7351 8-channel u1 hv7351 8-channel u2 hv7351 8-channel u16 t delay2 t delay3 t delay127 t delay128 e3 e1 e2 e127 e128 array probe 8-channel, 70v, 3a programmable high-voltage ultrasound-transmit beamformer downloaded from: http:///
hv7351 ds20005412a-page 2 ? 2015 microchip technology inc. package types (top view) hv7351 11 x 11 vqfn* dout2 av dd inv tck cs1 a0 7471 68 65 62 8077 81 7370 67 64 61 7976 72 69 66 63 7875 2730 33 36 39 2124 2831 34 37 40 2225 29 32 35 38 2326 710 13 16 19 14 811 14 17 20 25 9 12 15 18 36 5451 48 45 42 6057 5350 47 44 41 5956 52 49 46 43 5855 din2 size dv dd sck en cw cs2 d gnd trig tck v ll dout1 din1 a1 pv ss v nn v pf p gnd v pf d gnd v nf v pp pv dd p gnd p gnd d gnd dv dd pv ss p gnd v nn v nf d gnd pv dd v pp nc v rn pv ss tx2tx3 v pp pv dd p gnd tx1 v nn v nf v pf p gnd v pp v pp v nn v nn v pp v nn tx4 nc v rp pv ss tx7tx6 v pp pv dd p gnd tx8 v nn v nf v pf p gnd v pp v pp v nn v nn v pp v nn tx5 v sub * includes exposed thermal pad (ep); see table 2-1 . downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 3 hv7351 block diagram inven/ld cw clk 16/32 bit serial shift reg. inven/ld cw clk 16/32 bit serial shift reg. inv en/ld cw clk 16/32 bit serial shift reg. inven/ld cw clk 16/32 bit serial shift reg. divide by 2 6-bit counter divide by n n=1to64 linear regulator linear regulator en en 10-bit delay counter divide by 2 v ll to v dd translator - + p gnd p gnd v pf v pf v nf v nf pv ss pv dd pv ss pv dd v pp v pf v rn v rp v nf v nn v pp tx1v nn p gnd pv dd pv ss v pp tx8v nn p gnd cwf cw pinnin control logic cwf cw pinnin control logic rtz gate driver supply voltages 6-bit counter divide by n n=1to64 en en 10-bit delay counter 8 10-bit registers for delay counters 6-bit for divide by n 16/32-bit register pattern 4 16/32-bit register pattern 3 16/32-bit register pattern 2 16/32-bit register pattern 1 16/32-bit register pattern 4 16/32-bit register pattern 3 16/32-bit register pattern 2 16/32-bit register pattern 1 p-ch. registers n-ch. registers decoder v pf v rn v pp v nf v nn v rp v ll av dd dv dd en size sck din1 dout1 a0a1 din2 dout2 cw inv trig tck d gnd a gnd v sub cs2 cs1 tck downloaded from: http:///
hv7351 ds20005412a-page 4 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 5 hv7351 1.0 electrical characteristics absolute maximum ratings ? positive logic supply (v ll )............................................................................................................................ -0 .5v to 5.5v positive logic supply voltage (dv dd )............................................................................................................ -0.5v to 5.5v positive gate drive supply voltage (pv dd ) ................................................................................................... -0.5v to 5.5v positive analog supply voltage (av dd )......................................................................................................... -0.5v to 5.5v negative gate drive supply voltage (pv ss ) ................................................................................................ +0.5v to -5.5v high-voltage positive supply voltage (v pp ) ................................................................................................. -0.5v to +80v high-voltage negative supply voltage (v nn ) ............................................................................................... +0.5v to -80v differential high voltage supply (v pp - v nn )............................................................................................................+160v positive floating supply voltage (v pf ) .................................................................................................. v pp C 6.0v to v pp negative floating supply voltage (v nf ).................................................................................................v nn to v nn +6.0v positive supply for v nf regulator (v rp )............................................................................................................. 0v to 15v negative supply for v pf regulator (v rn ) .......................................................................................................... 0v to -15v operating temperature ......................................................................................................... ..................-40c to +125c storage temperature ............................................................................................................ ...................-65c to +150c esd rating all pins ............................................................................................................ .................................. 0.75 kv ? notice: stresses above those listed under maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. exposure to maximum rating conditions for e xtended periods may affect device reliability. table 1-1: operating supply voltages electrical specifications: unless otherwise specified: t a = +25c. boldface specifications apply over the t a range of -20 to +85c. parameter sym. min. typ. max. units conditions positive high voltage supply v pp 3.0 70 v note 1 negative high voltage supply v nn -70 -3.0 v logic interface voltage v ll 2.85 3.30 3.6 v low-voltage positive analog supply voltage av dd 4.75 5.00 5.25 v low-voltage positive digital supply voltage dv dd 4.75 5.00 5.25 v low-voltage positive gate drive supply voltage pv dd 4.75 5.00 5.25 v low-voltage negative gate drive supply voltage pv ss -5.25 -5.00 -4.75 v low-voltage positive supply for v nf regulator v rp 4.75 12 v low-voltage negative supply for v pf regulator v rn -12 -4.75 v reference voltage logic trip point for tck pin tck 0.4v ll 0.5v ll 0.6v ll v tck/tck input current i tck /i tck 1 0 a i tck = 0 to v ll , t a = +25c ( note 1 ) note 1: specification is obtained by characterization and is not 100% tested. downloaded from: http:///
hv7351 ds20005412a-page 6 ? 2015 microchip technology inc. table 1-2: regulator outputs parameter sym. min. typ. max. units conditions positive floating gate drive voltage v pf v pp -5.25 v pp -5.00 v pp - 4.00 v 4x1 f ceramic capacitors across v pf and v pp negative floating gate drive voltage v nf v nn +4.00 v nn +5.00 v nn + 5.25 v 4x1 f ceramic capacitors across v nf and v nn electrical characteristics electrical specifications: unless otherwise specified, v ll = 3.3v, av dd = dv dd = pv dd = v rp = 5.0v, pv ss = v rn = -5.0v, v pp = +70v, v nn = -70v, t a = +25c. parameter sym. min. typ. max. units conditions v ll quiescent current i vllq 384 500 a en = low, all inputs are static av dd quiescent current i avddq 1 23 0 a e n = l o w , all inputs are static dv dd quiescent current i dvddq 1 23 0 pv dd quiescent current i pvddq 7 01 0 0 v rp quiescent current i vrpq 0 . 3 6 a e n = l o w , all inputs are static v rn quiescent current i vrnq - 0 . 0 1 6 pv ss quiescent current i pvssq -85 -45 a en = low, all inputs are static v pp quiescent current i vppq 2 . 6 6 a e n = l o w , all inputs are static v nn quiescent current i vnnq - 1 . 6 6 v ll enabled quiescent current i vllen 390 500 a en = high, all inputs are static av dd enabled quiescent current i avdden 600 800 a en = high, all inputs are static dv dd enabled quiescent current i dvdden 2 25 5 pv dd enabled quiescent current i pvdden 44 100 a en = high, all inputs are static v rp enabled quiescent current i vrpen 450 650 a en = high, all inputs are static v rn enabled quiescent current i vrnen -650 -350 pv ss enabled quiescent current i pvssen -100 -44 a en = high, all inputs are static v pp enabled quiescent current i vppen 370 620 a en = high, all inputs are static v nn enabled quiescent current i vnnen -620 -420 v ll current at 80 mhz clock i vllcw 5 0 0 a v pp = +5.0v, v nn = -5.0v, en = high, cw = high, 80 mhz on tck, 0.5v ll on tck , all 8 channels active at 5.0 mhz, no load ( note 1 ) dv dd current at cw = 5 mhz i dvddcw 2 5m a v pp current at cw = 5 mhz i vppcw 1 4 1m a v nn current at cw = 5 mhz i vnncw 9 8m a note 1: specification is obtained by characterization and is not 100% tested. downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 7 hv7351 ac electrical characteristics electrical specifications: unless otherwise specified, v ll = 3.3v, av dd = dv dd = pv dd = v rp = 5.0v, pv ss = v rn = -5.0v, v pp = +70v, v nn = -70v, t a = +25c. parameter sym. min. typ. max. units conditions transmit clock frequency f tck 02 0 0 m h z serial clock frequency f sck 0 80 mhz no daisy chain 0 70 daisy chained ( note 2 ) set-up time data into sck t su-din 2n s note 1 hold time sck to data in t h-din 2n s note 1 set-up time cs1 low to sck t su-cs1 2n s note 2 set-up time cs2 low to sck t su-cs2 2n s note 2 set-up time from trig fall to tck rise edge t su-trig 2n s note 2 trig pulse width t w-trig 2xtck cycle note 2 sck to data out low to high delay time t lhdo 3 9 12 ns for dout1 ( note 1 ) 3 9 10 for dout2 ( note 1 ) sck to data out high to low delay time t hldo 3 9 12 ns for dout1 ( note 1 ) 3 9 10 for dout2 ( note 1 ) a1a0 pulse width t wa1a0 t w-trig +40 ns note 2 set-up time a1a0 to trig rising edge t sua1a0 2 0n s note 1 hold time a1a0 to trig falling edge t ha1a0 2 0n s device enable time t en-on 1 ms 1.0 f capacitor on every v pf and v nf pin ( note 1 ) device disable time t en-off 1 0 0n s note 1 output rise time from 0v to +hv t r1 9 13 ns load = 330 pf||2.5 k ? output fall time from 0v to -hv t f1 91 3n s damping output rise time from -hv to 0v t r2 91 3n s damping output fall time from +hv to 0v t f2 91 3n s output rise time from -hv to +hv t r3 1 72 3n s output fall time from +hv to -hv t f3 1 72 3n s cw output rise time t rcw 91 6n s v pp = +5.0v, v nn = -5.0v load = 330 pf||2.5 k ? cw output fall time t fcw 91 6n s note 1: specification is obtained by characterization and is not 100% tested. 2: specification is for design guidance only. downloaded from: http:///
hv7351 ds20005412a-page 8 ? 2015 microchip technology inc. output propagation delay rise time 1 t dr1 11 14 18 ns no load output propagation delay fall time 1 t df1 11 14 18 ns output propagation delay rise time 2 t dr2 12 15 19 ns output propagation delay fall time 2 t df2 11 15 18 ns output propagation delay rise time 3 t dr3 12 15 19 ns output propagation delay fall time 3 t df3 11 15 18 ns cw output propagation delay time from low to high t dcwlh 10 13 17 ns v pp = +5.0v, v nn = -5.0v no load cw output propagation delay time from high to low t dcwhl 10 14 17 ns delay time matching ? t dcwhl 0.7 ns p to n, channel-to-channel matching delay jitter on rise or fall t jcw 1 3p s v pp = +5.0v, v nn = -5.0v, load = 50 ??? note 2 ? latency lat 3.5 tck note 2 output p-channel mosfet to v pp , cw = 0 output saturation current i out 2.2 3.2 a output on-resistance r on 4 . 2 ? i out = 100 ma output capacitance c oss 6 2p f v pp - v out = 25v, f = 1.0 mhz ( note 2 ) output n-channel mosfet to v nn , cw = 0 output saturation current i out 2.2 3.2 a output on-resistance r on 2 . 4 ? i out = -100 ma output capacitance c oss 5 0p f v nn - v out = -25v, f = 1.0 mhz ( note 2 ) output p-channel mosfet to v pp , cw = 1 output saturation current i out 1.2 1.5 a output on-resistance r on 8 ? i out = 100 ma output capacitance c oss 6 2p f v pp - v out = 25v, f = 1.0 mhz ( note 2 ) ac electrical characteristics (continued) electrical specifications: unless otherwise specified, v ll = 3.3v, av dd = dv dd = pv dd = v rp = 5.0v, pv ss = v rn = -5.0v, v pp = +70v, v nn = -70v, t a = +25c. parameter sym. min. typ. max. units conditions note 1: specification is obtained by characterization and is not 100% tested. 2: specification is for design guidance only. downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 9 hv7351 output n-channel mosfet to v nn , cw = 1 output saturation current i out 1.2 1.5 a output on-resistance r on 6 . 6 ? i out = -100 ma output capacitance c oss 5 0p f v nn - v out = -25v, f = 1.0 mhz ( note 2 ) damping p-channel mosfet to p gnd output saturation current i out 2.2 3.2 a output on-resistance r on 4 ? i out = 100 ma output capacitance c oss 6 2p f v pp - v out = 25v, f = 1.0 mhz ( note 2 ) damping n-channel mosfet to p gnd output saturation current i out 2.2 3.2 a output on-resistance r on 2 . 3 ? i out = -100 ma output capacitance c oss 5 0p f v nn - v out = -25v, f = 1.0 mhz ( note 2 ) logic inputs clock input current i tck 1.0 a voltage 0 to v ll clock input high voltage v ih_tck v tck + 0.15 v ll vt ck = 0.5v ll ( note 2 ) clock input low voltage v il_tck 0 v tck - 0.15 v logic input high voltage v ih 0.8v ll v ll v for all logic inputs except clock inputs logic input low voltage v il 00 . 2 v ll v input logic high current i ih 1 a input logic low current i il -1 a output logic low voltage v ol 00 . 7v i out = 0 to -10 ma output logic high voltage v oh v ll - 0.7 v ll vi out = 0 to 10 ma input logic capacitance c in 5 . 0p f note 2 ac electrical characteristics (continued) electrical specifications: unless otherwise specified, v ll = 3.3v, av dd = dv dd = pv dd = v rp = 5.0v, pv ss = v rn = -5.0v, v pp = +70v, v nn = -70v, t a = +25c. parameter sym. min. typ. max. units conditions note 1: specification is obtained by characterization and is not 100% tested. 2: specification is for design guidance only. downloaded from: http:///
hv7351 ds20005412a-page 10 ? 2015 microchip technology inc. temperature specifications electrical specifications: unless otherwise specified, v ll = 3.3v, av dd = dv dd = pv dd = v rp = 5.0v, pv ss = v rn = -5.0v, v pp = +70v, v nn = -70v, t a = +25c. parameters sym. min. typ. max. units conditions temperature ranges operating ambient temperature range t a -40 +125 c storage temperature range t a -65 +150 c maximum junction temperature t j -40 +150 c package thermal resistances thermal resistance, 80l-11x11 vqfn ? ja 1 4 c / w table 1-3: logic truth table mode inputs outputs comments en cw 10-bit counter inv nin pin n-ch. p-ch. rtz non-cw mode. outputs not inverted. outputs are controlled by data in the shift registers 10 xx 00 off off on return-to-zero (rtz) is activated when nin and pin are both low. output is pulled to ground through a series diode. 10 x 001 off on off not inverted. logic 1 in the p-channel register turns on the output p-channel mosfet. 10 x 010 on off off not inverted. logic 1 in the n-channel register turns on the output n-channel mosfet. 10 xx 11 off off off avoids cross overcurrent. a logic 1 in both p- and n- channel registers will put the output in a high z state. non-cw mode. outputs are inverted. outputs are controlled by data in the shift registers 10 x 101 on off off transmit pattern is inverted 10 x 110 off on off cw mode. output follows f cw 1 x all 1 x x x off off off if 10-bit counter reach all 1 , then the channel will be turned off. 11 not all 1 x x x off/ on on/ off off the channel's output fol- lows the f cw signal. the shift registers for pin and nin remain static to save power. device disabled 0 xxxxxo f fo f fo f fh i g h z s t a t e legend: x = dont care. downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 11 hv7351 1.1 timing diagrams figure 1-1: timing diagram of 3-level, 1-cycle bipolar rtz tx pulse. figure 1-2: timing diagram of 2-level 2-cycle bipolar, non-rtz tx pulses with damping. tck 0v 3.3v trig tx1 0v +70v internal clk (forn=2) 0v example with tx2 delay having two tck cycles more than tx1 tck = 1.65v (0.5v ll ) tx2 delay time set by tx2 10-bit counter delay time set by tx1 10-bit counter t wtrig needs to be at least 2 rising edges of tck 0v 3.3v 0v 3.3v -70v +70v -70v 3.5 tck cycles t wtrig t su-trig t dr1 t df2 t df1 t r1 t f2 t dr2 10% 10% 90% 90% 10% 10% 90% 90% t f1 t r2 example with tx2 delay having one tck cycle more than tx1 delay time set by tx2 10-bit counter 3.5 tck cycles t su-trig t wtrig needs to be at least 2 rising edges of tck t wtrig delay time set by tx1 10-bit counter t df3 90% 10% 10% 90% t f3 t r3 t dr3 tck 0v 3.3v trig tx1 0v +70v internal clk (for n = 2) 0v tck=1.65v(0.5v ll ) tx2 0v 3.3v 0v 3.3v -70v +70v -70v downloaded from: http:///
hv7351 ds20005412a-page 12 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 13 hv7351 2.0 pin description the descriptions of the pins are listed in tab l e 2 - 1 . table 2-1: pin function table pin symbol description 1a v dd positive analog supply voltage (+5.0v) 2 din2 serial data in for delay counters and frequency divider 3c s 2 activates din2. input logic high = off, input logic low = on. 4 size sets pattern width to either 16-bits or 32-bits. logic low = 16-bits, logic high = 32-bits. 5 inv inverts the tx output waveform. see tab l e 1 - 3 for details. 6 cw activates cw mode. logic low = non-cw mode, logic high = cw mode. see table 1-3 for details. 7 dout2 data out for delay counters and frequency divider 8 en enables and disables device. logic low = off, logic high = on. 9 sck serial clock input for serial shift registers 10, 50 dv dd positive digital supply voltage (+5.0v) 11, 43, 51, 58 d gnd digital ground 12 trig toggles all tx outputs to transmit. needs to be high for two rising edges of tck. delay counters will start on the rising edge of the tck pin right after the falling edge of the trig signal. see section 1.1 timing diagrams for details. 13 tck the tck and tck pins can be driven by lvds or sstl types of output in a differential manner. the tck pin can be driven by lvcmos single-ended output, while setting the tck to gnd (or dc value of 0.4v to 0.6v). the logic trip point is on the tck rising edge and on the tck falling edge, crossing in the differential manner. in the single-ended case, the trip point is on the tck rising edge. 14 tck 15 v ll logic interface supply voltage (3.3v) 16 cs1 activates din1. input logic high = off, input logic low = on 17 dout1 data out for p-channel and n-channel pattern registers 18 a0 decoded to select 1 of 4 patterns to be loaded 19 a1 20 din1 serial data in for p-channel and n-channel pattern registers 21 v rn negative supply for v pf regulator (-5.0v) 22, 49, 52, 79 pv dd positive gate drive supply voltage for rtz output transistors (+5.0v) 23, 24, 46, 48, 53, 55, 77, 78 p gnd power ground path for rtz output transistors 25, 47, 54, 76 pv ss negative gate drive supply voltage for rtz output transistors (-5.0v) 26, 45, 56, 75 v pf linear regulator output gate drive voltage for the p-channel output transistors. a low voltage 1.0 f ceramic capacitor needs to be connected across every v pf and v pp pins. there are four capacitors required in total. 27 nc no connection 28, 42, 59, 73 v nf linear regulator output gate drive voltage for the n-channel output transistors. a low voltage 1.0 f ceramic capacitor needs to be connected across every v nf to v nn pins. there are four capacitors required in total. 29, 34, 35, 40, 41, 60, 61, 66, 67, 72 v nn negative high voltage supply (-3.0v to -70v) 30 tx1 transmit pulser outputs for channel 1 31, 32, 37, 38, 44, 57, 63, 64, 69, 70 v pp positive high voltage supply (+3.0v to +70v) downloaded from: http:///
hv7351 ds20005412a-page 14 ? 2015 microchip technology inc. 33 tx2 transmit pulser outputs for channel 2 36 tx3 transmit pulser outputs for channel 3 39 tx4 transmit pulser outputs for channel 4 62 tx5 transmit pulser outputs for channel 5 65 tx6 transmit pulser outputs for channel 6 68 tx7 transmit pulser outputs for channel 7 71 tx8 transmit pulser outputs for channel 8 74 nc no connection 80 v rp positive supply for v nf regulator (+5.0v) 81 v sub exposed center pad must be externally connected to the ground (gnd, 0v) on pcb. (d gnd ). table 2-1: pin function table (continued) pin symbol description downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 15 hv7351 3.0 device description 3.1 loading data into the four 16/32 bit pattern registers a detailed circuit diagram of the pattern registers is shown in figure 3-1 . there are four programmable pat- terns that can be stored. one of four patterns can be selected via the two input logic decoder pins, a1 and a0. data can be loaded on the selected pattern. each pattern can be either 16- or 32-bits wide. the size pin determines whether they are 16- or 32-bits wide. size = h will set the pattern to be 32-bits wide while size = l will set it to 16-bits wide. din1 is the input data for the register. when cs1 is high, data will not be shifted in. data is shifted in only when cs1 is low. figure 3-1: pattern register circuit diagram. with size = h, the circuit is effectively a 64-bit serial shift register. the data first enters into the p-channel register and continues to be shifted though to the n-channel register. data is clocked in during the rising edge of the clock. there is no activity during the falling edge of the clock. the din1 data enters into the s64 of p-channel register and exits the s1 of n-channel register from dout1. the spi writing operation of the waveform pattern registers are lsb first. example 3-1: data is shifted in during the rising edge of the clock. s1 is the first bit shifted in, entering the p-channel register. after 64 clock cycles, s1 will be located in the n-chan- nel register, as shown in figure 3-2 . it will also be clocked out to dout1. figure 3-2: waveform pattern register. 2to4 decoder dout1 sck din1 sizeen din sck size 16-/32-bits shift register p-ch. pattern 1 cs1 16-/32-bits shift register p-ch. pattern 2 16-/32-bits shift register p-ch. pattern 3 16/32 bits shift register p-ch. pattern 4 16/32 bits shift register n-ch. pattern 4 16-/32-bits shift register n-ch. pattern 3 16-/32-bits shift register n-ch. pattern 2 16-/32-bits shift register n-ch. pattern 1 sizeen din sck sizeen din sck sizeen din sck a1 a0 cs1 a1 a0 cs1 a1 a0 cs1 a1 a0 cs1 a1a0 a1 a0 cs1 a1 a0 cs1 a1 a0 cs1 a1 a0 cs1 for: size = high, 32-bits wide (size = low, 16-bits wide) a1 = a0 = low, pattern 1 selected cs1 = low, data can be shifted in 64-bit serial shift register: 32 bits for the p-channel and 32 bits for the n-channel dout1 din1 sck 32 bits for p-ch pattern 1 32 bits for n-ch pattern 1 32 bits for p-ch pattern 1 32 bits for n-ch pattern 1 s64 s63 s34 s33 s31 s32 s2 s1 downloaded from: http:///
hv7351 ds20005412a-page 16 ? 2015 microchip technology inc. a 2-to-4 decoder is provided to select which of the four patterns is to be used for all of the outputs. logic inputs a1 and a0 determine which patterns are selected, fol- lowing table 3-1 . once a1 and a0 are set, a rising edge on the trigger logic input pin will automatically load the selected pattern to all of the outputs. 3.2 loading data into the delay counters and the divide-by-n counter each output channel (tx) has its own programmable 10-bit delay counter. for 8 channels, 80 bits are needed. a 6-bit divide-by-n counter is also provided to program the desired tx frequency. to program all the individual delay counters and the divide-by-n counter, an 86-bit serial shift register is provided. it uses the same clock input that the pattern registers uses. din2 is the input data for this register. when cs2 is high, data will not be shifted in. data is shifted in only when cs2 is low. as shown in figure 3-3 , the data first enters into the 10-bit register for the tx8 delay counter and continues to be shifted through to the 6-bit register for the divide-by-n counter. data is clocked in during the rising edge of the clock. there is no activity during the falling edge of the clock. the msb bit in the 6-bit divide-by-n register is clocked out into dout2 for cascading multi- ple devices, if desired. figure 3-3: delay and divide-by-n registers. 3.3 10-bit delay counter the tck and tck pins are the input clock for the 10-bit delay counter. the maximum capable clock frequency is up to 200 mhz. the counter counts upward. table 3-1: decoder truth table logic decoder input pattern selected a1 a2 00 1 01 2 10 3 11 4 10 bits tx8 10 bits tx7 10 bits tx6 10 bits tx5 10 bits tx4 dout2 lsb din2 sck lsb 86-bit serial shift register: 80 bits for the delay counters and 6 bits for the divide by n 10 bits tx3 10 bits tx2 10 bits tx4 6bits divide by n 10 bits tx8 delay counter 10 bits tx7 delay counter 6 bits divide by n lsb msb msb msb s86 s85 s84 s83 s82 s81 s80 s79 s78 s77 s76 s75 s74 s73 s72 s71 s70 s69 s68 s67 s6 s5 s4 s3 s2 s1 table 3-2: delay counter msb lsb delay time 000000000 0 1023 tck cycles 000000000 1 1022 tck cycles 000000001 0 1021 tck cycles 000000001 1 1020 tck cycles 111111110 0 3 tck cycles 111111110 1 2 tck cycles 111111111 0 1 tck cycle 111111111 1 no trigger downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 17 hv7351 3.4 6-bit divide-by-n counter the tck and tck pins are the input clock for the 6-bit divide-by-n counter. it generates the clock frequency for the 16-/32-bit serial shift register for the output p- and n-channel patterns. each clock cycle will set the tx output to be either at v pp , v nn , ground or high- impedance, depending on what was preprogrammed in their corresponding registers. table 3-3: 6-bit divide-by-n counter register msb lsb output shift register clock frequency 000000 f tck 64 000001 f tck 63 000010 f tck 62 000011 f tck 61 111100 f tck 4 111101 f tck 3 111110 f tck 2 111111 f tck 1 downloaded from: http:///
hv7351 ds20005412a-page 18 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 19 hv7351 4.0 packaging information 4.1 package marking information legend: xx...x product code or customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week 01) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. package may or may not in clude the corporate logo. 3 e 3 e 80-lead vqfn (11x11x1.0 mm) example hv7351k6 1508256 downloaded from: http:///
hv7351 ds20005412a-page 20 ? 2015 microchip technology inc. note: for the most current package drawings, see the microchip packaging specification at www.microchip.com/packaging. downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 21 hv7351 appendix a: revision history revision a (june 2015) original release of this document. downloaded from: http:///
hv7351 ds20005412a-page 22 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 23 hv7351 product identification system to order or obtain information, e. g., on pricing or delivery, refer to the factory or the listed sales office . part no. xx package device device: hv7351: programmable high-voltage, ultrasound-transmit beamformer package: k6 = very thin plastic quad flat pack, no lead package C 11.00x11.00x1.0 mm body, 0.50 mm pitch, 80-lead (vqfn) environmental: g = lead (pb)-free/rohs-compliant package examples: a) HV7351K6-G: programmable high-voltage ultrasound-transmit beamformer, 80ld 11x11 mm vqfn package -x environmental downloaded from: http:///
hv7351 ds20005412a-page 24 ? 2015 microchip technology inc. notes: downloaded from: http:///
? 2015 microchip technology inc. ds20005412a-page 25 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip tec hnology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered trademar ks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-63277-402-6 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchips code protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory an d analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 == downloaded from: http:///
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